[llvm] 6c87ec4 - [AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 3 21:21:06 PST 2025
Author: Akshat Oke
Date: 2025-03-04T10:51:03+05:30
New Revision: 6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
URL: https://github.com/llvm/llvm-project/commit/6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d
DIFF: https://github.com/llvm/llvm-project/commit/6c87ec4f4d083a85ebcfbbda166ad4ba41d5da8d.diff
LOG: [AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.h
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/SIModeRegister.cpp
llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
llvm/test/CodeGen/AMDGPU/mode-register.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 1f2431fa34e9a..57297288eecb4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -352,6 +352,12 @@ class AMDGPUAnnotateUniformValuesPass
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
};
+class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
+public:
+ SIModeRegisterPass() {}
+ PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
+};
+
FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
ModulePass *createAMDGPUPrintfRuntimeBinding();
@@ -419,7 +425,7 @@ extern char &SIAnnotateControlFlowLegacyPassID;
void initializeSIMemoryLegalizerPass(PassRegistry&);
extern char &SIMemoryLegalizerID;
-void initializeSIModeRegisterPass(PassRegistry&);
+void initializeSIModeRegisterLegacyPass(PassRegistry &);
extern char &SIModeRegisterID;
void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 64e07e4041cd3..1050855176c04 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -112,6 +112,7 @@ MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
MACHINE_FUNCTION_PASS("si-lower-control-flow", SILowerControlFlowPass())
MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-lower-wwm-copies", SILowerWWMCopiesPass())
+MACHINE_FUNCTION_PASS("si-mode-register", SIModeRegisterPass())
MACHINE_FUNCTION_PASS("si-opt-vgpr-liverange", SIOptimizeVGPRLiveRangePass())
MACHINE_FUNCTION_PASS("si-optimize-exec-masking", SIOptimizeExecMaskingPass())
MACHINE_FUNCTION_PASS("si-optimize-exec-masking-pre-ra", SIOptimizeExecMaskingPreRAPass())
@@ -131,7 +132,6 @@ DUMMY_MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
DUMMY_MACHINE_FUNCTION_PASS("si-insert-waitcnts", SIInsertWaitcntsPass())
DUMMY_MACHINE_FUNCTION_PASS("si-late-branch-lowering", SILateBranchLoweringPass())
DUMMY_MACHINE_FUNCTION_PASS("si-memory-legalizer", SIMemoryLegalizerPass())
-DUMMY_MACHINE_FUNCTION_PASS("si-mode-register", SIModeRegisterPass())
DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
// TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it
// already exists.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 7bf6e8f671db8..ce3dcd920bce3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -536,7 +536,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUInsertDelayAluLegacyPass(*PR);
initializeSIInsertHardClausesPass(*PR);
initializeSIInsertWaitcntsPass(*PR);
- initializeSIModeRegisterPass(*PR);
+ initializeSIModeRegisterLegacyPass(*PR);
initializeSIWholeQuadModeLegacyPass(*PR);
initializeSILowerControlFlowLegacyPass(*PR);
initializeSIPreEmitPeepholePass(*PR);
diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
index 99aea52c184d6..dc723986badc7 100644
--- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
+++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
@@ -107,10 +107,8 @@ class BlockData {
namespace {
-class SIModeRegister : public MachineFunctionPass {
+class SIModeRegister {
public:
- static char ID;
-
std::vector<std::unique_ptr<BlockData>> BlockInfo;
std::queue<MachineBasicBlock *> Phase2List;
@@ -125,15 +123,7 @@ class SIModeRegister : public MachineFunctionPass {
bool Changed = false;
-public:
- SIModeRegister() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesCFG();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+ bool run(MachineFunction &MF);
void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
@@ -146,16 +136,32 @@ class SIModeRegister : public MachineFunctionPass {
void insertSetreg(MachineBasicBlock &MBB, MachineInstr *I,
const SIInstrInfo *TII, Status InstrMode);
};
+
+class SIModeRegisterLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ SIModeRegisterLegacy() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
} // End anonymous namespace.
-INITIALIZE_PASS(SIModeRegister, DEBUG_TYPE,
+INITIALIZE_PASS(SIModeRegisterLegacy, DEBUG_TYPE,
"Insert required mode register values", false, false)
-char SIModeRegister::ID = 0;
+char SIModeRegisterLegacy::ID = 0;
-char &llvm::SIModeRegisterID = SIModeRegister::ID;
+char &llvm::SIModeRegisterID = SIModeRegisterLegacy::ID;
-FunctionPass *llvm::createSIModeRegisterPass() { return new SIModeRegister(); }
+FunctionPass *llvm::createSIModeRegisterPass() {
+ return new SIModeRegisterLegacy();
+}
// Determine the Mode register setting required for this instruction.
// Instructions which don't use the Mode register return a null Status.
@@ -422,7 +428,20 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
}
}
-bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
+bool SIModeRegisterLegacy::runOnMachineFunction(MachineFunction &MF) {
+ return SIModeRegister().run(MF);
+}
+
+PreservedAnalyses SIModeRegisterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &AM) {
+ if (!SIModeRegister().run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ return PA;
+}
+
+bool SIModeRegister::run(MachineFunction &MF) {
// Constrained FP intrinsics are used to support non-default rounding modes.
// strictfp attribute is required to mark functions with strict FP semantics
// having constrained FP intrinsics. This pass fixes up operations that uses
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
index 8667934d70ff0..b3a4aa7b6c19a 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -passes si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
---
name: ftrunc_tonearest
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register.mir b/llvm/test/CodeGen/AMDGPU/mode-register.mir
index a918684056f65..aac6dcb01f3d9 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-mode-register %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-mode-register %s -o - | FileCheck %s
---
# check that the mode is changed to rtz from default rtn for interp f16
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