[llvm] 77f44a9 - [CodeGen][NewPM] Port MachineSink to NPM (#115434)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 3 02:19:41 PST 2025
Author: Akshat Oke
Date: 2025-03-03T15:49:37+05:30
New Revision: 77f44a964212a54ebc014a703c6787ae236b6ef4
URL: https://github.com/llvm/llvm-project/commit/77f44a964212a54ebc014a703c6787ae236b6ef4
DIFF: https://github.com/llvm/llvm-project/commit/77f44a964212a54ebc014a703c6787ae236b6ef4.diff
LOG: [CodeGen][NewPM] Port MachineSink to NPM (#115434)
Targets can set the EnableSinkAndFold option in CGPassBuilderOptions for
the NPM pipeline in buildCodeGenPipeline(... &Opts, ...)
Added:
llvm/include/llvm/CodeGen/MachineSink.h
Modified:
llvm/include/llvm/CodeGen/Passes.h
llvm/include/llvm/InitializePasses.h
llvm/include/llvm/Passes/CodeGenPassBuilder.h
llvm/include/llvm/Passes/MachinePassRegistry.def
llvm/include/llvm/Target/CGPassBuilderOption.h
llvm/lib/CodeGen/CodeGen.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/TargetPassConfig.cpp
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
llvm/test/CodeGen/AArch64/loop-sink.mir
llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
llvm/test/CodeGen/ARM/machine-sink-multidef.mir
llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineSink.h b/llvm/include/llvm/CodeGen/MachineSink.h
new file mode 100644
index 0000000000000..71bd7229b7598
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/MachineSink.h
@@ -0,0 +1,30 @@
+//===- MachineSink.h --------------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_MACHINESINK_H
+#define LLVM_CODEGEN_MACHINESINK_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class MachineSinkingPass : public PassInfoMixin<MachineSinkingPass> {
+ bool EnableSinkAndFold;
+
+public:
+ MachineSinkingPass(bool EnableSinkAndFold = false)
+ : EnableSinkAndFold(EnableSinkAndFold) {}
+
+ PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &);
+
+ void printPipeline(raw_ostream &OS,
+ function_ref<StringRef(StringRef)> MapClassName2PassName);
+};
+
+} // namespace llvm
+#endif // LLVM_CODEGEN_MACHINESINK_H
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h
index 0182f21bee5f5..5fa67a29ddbb6 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -353,7 +353,7 @@ namespace llvm {
extern char &EarlyMachineLICMID;
/// MachineSinking - This pass performs sinking on machine instructions.
- extern char &MachineSinkingID;
+ extern char &MachineSinkingLegacyID;
/// MachineCopyPropagation - This pass performs copy propagation on
/// machine instructions.
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 0850405bb101d..777cd8fb6e1eb 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -208,7 +208,7 @@ void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
void initializeMachineSchedulerLegacyPass(PassRegistry &);
-void initializeMachineSinkingPass(PassRegistry &);
+void initializeMachineSinkingLegacyPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
void initializeMachineUniformityAnalysisPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index bab034293a6d0..ed43f5333316c 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -52,6 +52,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineScheduler.h"
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -1044,7 +1045,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineSSAOptimization(
addPass(EarlyMachineLICMPass());
addPass(MachineCSEPass());
- addPass(MachineSinkingPass());
+ addPass(MachineSinkingPass(Opt.EnableSinkAndFold));
addPass(PeepholeOptimizerPass());
// Clean-up the dead code that may have been generated by peephole
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 92826ac8db2c5..d4129330f3395 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -190,6 +190,13 @@ MACHINE_FUNCTION_PASS("verify<machine-trace-metrics>", MachineTraceMetricsVerifi
#define MACHINE_FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER, \
PARAMS)
#endif
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "machine-sink", "MachineSinkingPass",
+ [](bool EnableSinkAndFold) {
+ return MachineSinkingPass(EnableSinkAndFold);
+ },
+ parseMachineSinkingPassOptions, "enable-sink-fold")
+
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"regallocfast", "RegAllocFastPass",
[](RegAllocFastPass::Options Opts) { return RegAllocFastPass(Opts); },
@@ -258,7 +265,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass)
DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
-DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h
index 13881f6dcf82b..f006ef1fcb40b 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -49,6 +49,7 @@ struct CGPassBuilderOption {
bool EnableBlockPlacementStats = false;
bool EnableGlobalMergeFunc = false;
bool EnableMachineFunctionSplitter = false;
+ bool EnableSinkAndFold = false;
bool MISchedPostRA = false;
bool EarlyLiveIntervals = false;
bool GCEmptyBlocks = false;
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 96db2dc94d5b8..380b5e484921b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -95,7 +95,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
initializeMachineSchedulerLegacyPass(Registry);
- initializeMachineSinkingPass(Registry);
+ initializeMachineSinkingLegacyPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
initializeMachineVerifierLegacyPassPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0dbf5605d0567..4f206a8a24432 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -15,6 +15,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/MapVector.h"
@@ -26,6 +27,8 @@
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CFG.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
+#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -42,6 +45,7 @@
#include "llvm/CodeGen/MachineSizeOpts.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -118,7 +122,7 @@ using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
namespace {
-class MachineSinking : public MachineFunctionPass {
+class MachineSinking {
const TargetSubtargetInfo *STI = nullptr;
const TargetInstrInfo *TII = nullptr;
const TargetRegisterInfo *TRI = nullptr;
@@ -132,6 +136,11 @@ class MachineSinking : public MachineFunctionPass {
AliasAnalysis *AA = nullptr;
RegisterClassInfo RegClassInfo;
TargetSchedModel SchedModel;
+ // Required for split critical edge
+ LiveIntervals *LIS;
+ SlotIndexes *SI;
+ LiveVariables *LV;
+ MachineLoopInfo *MLI;
// Remember which edges have been considered for breaking.
SmallSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>, 8>
@@ -189,30 +198,19 @@ class MachineSinking : public MachineFunctionPass {
bool EnableSinkAndFold;
public:
- static char ID; // Pass identification
-
- MachineSinking() : MachineFunctionPass(ID) {
- initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- MachineFunctionPass::getAnalysisUsage(AU);
- AU.addRequired<AAResultsWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addRequired<MachinePostDominatorTreeWrapperPass>();
- AU.addRequired<MachineCycleInfoWrapperPass>();
- AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
- AU.addPreserved<MachineCycleInfoWrapperPass>();
- AU.addPreserved<MachineLoopInfoWrapperPass>();
- AU.addRequired<ProfileSummaryInfoWrapperPass>();
- if (UseBlockFreqInfo)
- AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
- AU.addRequired<TargetPassConfig>();
- }
-
- void releaseMemory() override {
+ MachineSinking(bool EnableSinkAndFold, MachineDominatorTree *DT,
+ MachinePostDominatorTree *PDT, LiveVariables *LV,
+ MachineLoopInfo *MLI, SlotIndexes *SI, LiveIntervals *LIS,
+ MachineCycleInfo *CI, ProfileSummaryInfo *PSI,
+ MachineBlockFrequencyInfo *MBFI,
+ const MachineBranchProbabilityInfo *MBPI, AliasAnalysis *AA)
+ : DT(DT), PDT(PDT), CI(CI), PSI(PSI), MBFI(MBFI), MBPI(MBPI), AA(AA),
+ LIS(LIS), SI(SI), LV(LV), MLI(MLI),
+ EnableSinkAndFold(EnableSinkAndFold) {}
+
+ bool run(MachineFunction &MF);
+
+ void releaseMemory() {
CEBCandidates.clear();
CEMergeCandidates.clear();
}
@@ -290,21 +288,47 @@ class MachineSinking : public MachineFunctionPass {
bool registerPressureExceedsLimit(const MachineBasicBlock &MBB);
};
+class MachineSinkingLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ MachineSinkingLegacy() : MachineFunctionPass(ID) {
+ initializeMachineSinkingLegacyPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addRequired<MachinePostDominatorTreeWrapperPass>();
+ AU.addRequired<MachineCycleInfoWrapperPass>();
+ AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
+ AU.addPreserved<MachineCycleInfoWrapperPass>();
+ AU.addPreserved<MachineLoopInfoWrapperPass>();
+ AU.addRequired<ProfileSummaryInfoWrapperPass>();
+ if (UseBlockFreqInfo)
+ AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
+ AU.addRequired<TargetPassConfig>();
+ }
+};
+
} // end anonymous namespace
-char MachineSinking::ID = 0;
+char MachineSinkingLegacy::ID = 0;
-char &llvm::MachineSinkingID = MachineSinking::ID;
+char &llvm::MachineSinkingLegacyID = MachineSinkingLegacy::ID;
-INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
- false)
+INITIALIZE_PASS_BEGIN(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking",
+ false, false)
INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
- false)
+INITIALIZE_PASS_END(MachineSinkingLegacy, DEBUG_TYPE, "Machine code sinking",
+ false, false)
/// Return true if a target defined block prologue instruction interferes
/// with a sink candidate.
@@ -728,28 +752,87 @@ void MachineSinking::FindCycleSinkCandidates(
}
}
-bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+MachineSinkingPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto *DT = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ auto *PDT = &MFAM.getResult<MachinePostDominatorTreeAnalysis>(MF);
+ auto *CI = &MFAM.getResult<MachineCycleAnalysis>(MF);
+ auto *PSI = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF)
+ .getCachedResult<ProfileSummaryAnalysis>(
+ *MF.getFunction().getParent());
+ auto *MBFI = UseBlockFreqInfo
+ ? &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF)
+ : nullptr;
+ auto *MBPI = &MFAM.getResult<MachineBranchProbabilityAnalysis>(MF);
+ auto *AA = &MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager()
+ .getResult<AAManager>(MF.getFunction());
+ auto *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF);
+ auto *SI = MFAM.getCachedResult<SlotIndexesAnalysis>(MF);
+ auto *LV = MFAM.getCachedResult<LiveVariablesAnalysis>(MF);
+ auto *MLI = MFAM.getCachedResult<MachineLoopAnalysis>(MF);
+ MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI,
+ MBFI, MBPI, AA);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserve<MachineCycleAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
+ return PA;
+}
+
+void MachineSinkingPass::printPipeline(
+ raw_ostream &OS, function_ref<StringRef(StringRef)> MapClassName2PassName) {
+ OS << MapClassName2PassName(name()); // ideally machine-sink
+ if (EnableSinkAndFold)
+ OS << "<enable-sink-fold>";
+}
+
+bool MachineSinkingLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
+ bool EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
+
+ auto *DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ auto *PDT =
+ &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
+ auto *CI = &getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
+ auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
+ auto *MBFI =
+ UseBlockFreqInfo
+ ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
+ : nullptr;
+ auto *MBPI =
+ &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
+ auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+ // Get analyses for split critical edge.
+ auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ auto *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
+ auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
+ auto *SI = SIWrapper ? &SIWrapper->getSI() : nullptr;
+ auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>();
+ auto *LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
+ auto *MLIWrapper = getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
+ auto *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
+
+ MachineSinking Impl(EnableSinkAndFold, DT, PDT, LV, MLI, SI, LIS, CI, PSI,
+ MBFI, MBPI, AA);
+ return Impl.run(MF);
+}
+
+bool MachineSinking::run(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n");
STI = &MF.getSubtarget();
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
MRI = &MF.getRegInfo();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- PDT = &getAnalysis<MachinePostDominatorTreeWrapperPass>().getPostDomTree();
- CI = &getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
- PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
- MBFI = UseBlockFreqInfo
- ? &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI()
- : nullptr;
- MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
+
RegClassInfo.runOnMachineFunction(MF);
- TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
- EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
bool EverMadeChange = false;
@@ -767,8 +850,8 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
MachineDomTreeUpdater MDTU(DT, PDT,
MachineDomTreeUpdater::UpdateStrategy::Lazy);
for (const auto &Pair : ToSplit) {
- auto NewSucc =
- Pair.first->SplitCriticalEdge(Pair.second, *this, nullptr, &MDTU);
+ auto NewSucc = Pair.first->SplitCriticalEdge(
+ Pair.second, {LIS, SI, LV, MLI}, nullptr, &MDTU);
if (NewSucc != nullptr) {
LLVM_DEBUG(dbgs() << " *** Splitting critical edge: "
<< printMBBReference(*Pair.first) << " -- "
@@ -858,6 +941,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
MRI->clearKillFlags(I);
RegsToClearKillFlags.clear();
+ releaseMemory();
return EverMadeChange;
}
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 5d9da9df9092a..ea5e43ff12166 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -324,7 +324,7 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID,
if (StandardID == &MachineLICMID)
return applyDisable(TargetID, DisablePostRAMachineLICM);
- if (StandardID == &MachineSinkingID)
+ if (StandardID == &MachineSinkingLegacyID)
return applyDisable(TargetID, DisableMachineSink);
if (StandardID == &PostRAMachineSinkingID)
@@ -1316,7 +1316,7 @@ void TargetPassConfig::addMachineSSAOptimization() {
addPass(&EarlyMachineLICMID);
addPass(&MachineCSELegacyID);
- addPass(&MachineSinkingID);
+ addPass(&MachineSinkingLegacyID);
addPass(&PeepholeOptimizerLegacyID);
// Clean-up the dead code that may have been generated by peephole
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index a0fb2bcfbce14..e7157a3192164 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -122,6 +122,7 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
+#include "llvm/CodeGen/MachineSink.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
@@ -1430,6 +1431,11 @@ parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
inconvertibleErrorCode());
}
+Expected<bool> parseMachineSinkingPassOptions(StringRef Params) {
+ return PassBuilder::parseSinglePassOption(Params, "enable-sink-fold",
+ "MachineSinkingPass");
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
index 229fecf2d3b10..b3634720a0c6c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
@@ -509,7 +509,7 @@ void NVPTXPassConfig::addMachineSSAOptimization() {
addPass(&EarlyMachineLICMID);
addPass(&MachineCSELegacyID);
- addPass(&MachineSinkingID);
+ addPass(&MachineSinkingLegacyID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
addPass(&PeepholeOptimizerLegacyID);
diff --git a/llvm/test/CodeGen/AArch64/loop-sink.mir b/llvm/test/CodeGen/AArch64/loop-sink.mir
index 36d39ffbadc29..de81d99369394 100644
--- a/llvm/test/CodeGen/AArch64/loop-sink.mir
+++ b/llvm/test/CodeGen/AArch64/loop-sink.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=machine-sink -sink-insts-to-avoid-spills -aarch64-enable-sink-fold=true %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple aarch64 -passes="machine-sink<enable-sink-fold>" -sink-insts-to-avoid-spills %s -o - 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
index be5737d297b29..f146c4436bbfa 100644
--- a/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
+++ b/llvm/test/CodeGen/AArch64/sink-and-fold-preserve-debugloc.mir
@@ -1,4 +1,6 @@
# RUN: llc %s -run-pass=machine-sink --aarch64-enable-sink-fold=true -o - | FileCheck %s
+
+# RUN: llc %s -passes="machine-sink<enable-sink-fold>" -o - | FileCheck %s
--- |
target triple = "aarch64-linux"
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
index 329f296712160..0732648f6c7a1 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -passes="function(machine-function(machine-sink))" -o - %s | FileCheck %s
+
---
name: machine-sink-temporal-divergence
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/ARM/machine-sink-multidef.mir b/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
index 737ca824265d6..485e659a53ab6 100644
--- a/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
+++ b/llvm/test/CodeGen/ARM/machine-sink-multidef.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -run-pass=machine-sink -mtriple=arm-none-eabi | FileCheck %s
+# RUN: llc %s -o - -passes=machine-sink -mtriple=arm-none-eabi | FileCheck %s
+
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "arm-none-unknown-eabi"
diff --git a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
index f994493def0c9..fa05362b8e1e5 100644
--- a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
+++ b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
@@ -1,5 +1,7 @@
# RUN: llc -mtriple=hexagon -run-pass machine-sink -o - %s | FileCheck %s
+# RUN: llc -march=hexagon -passes machine-sink -o - %s | FileCheck %s
+
# Test that MachineSink does not sink F2_conv_w2sf.
# CHECK: name:{{.*}} main
# CHECK: J2_call @feclearexcept
diff --git a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
index fe50d05ab93a5..ee16a8c69afb7 100644
--- a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
+++ b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
@@ -2,6 +2,8 @@
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \
# RUN: -run-pass=machine-sink | FileCheck %s
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \
+# RUN: -passes=machine-sink | FileCheck %s
--- |
; ModuleID = 'sink-down-more-instructions-1.ll'
source_filename = "sink-down-more-instructions-1.c"
diff --git a/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir b/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
index ef006fca60a40..8f5c763e95020 100644
--- a/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
+++ b/llvm/test/CodeGen/RISCV/MachineSink-implicit-x0.mir
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=riscv32 %s -run-pass=machine-sink -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 %s -passes=machine-sink -o - | FileCheck %s
# Verify that sinking of '%20:gpr = LUI 1, implicit $x0' is not inhibited by
# the implicit use of '$x0'.
diff --git a/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir b/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
index 8516cc9114c76..7b62c0b49b816 100644
--- a/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
+++ b/llvm/test/CodeGen/SystemZ/machinesink-dead-cc.mir
@@ -1,6 +1,9 @@
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -run-pass=machine-sink %s -o - \
# RUN: -verify-machineinstrs | FileCheck %s
#
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -O3 -passes=machine-sink %s -o - \
+# RUN: -verify-machineinstrs | FileCheck %s
+#
# Test that the AGHIK can be sunk into %bb.4. It has a def of CC, but it is dead.
--- |
diff --git a/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir b/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
index 643c557db77f7..20207311e66cd 100644
--- a/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
+++ b/llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
@@ -2,6 +2,9 @@
# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=machine-sink %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=mir-debugify,machine-sink,mir-strip-debug %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -passes=machine-sink %s -o - | FileCheck %s
+# TODO: add test with mir-debugify once it is ported
+
# Verify that machine-sink pass is debug invariant wrt to given input. Since
# the pass examines MemOperands the IR is required for the original bug to
# trigger.
diff --git a/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir b/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
index 73a571dbf150f..b7df7983073e8 100644
--- a/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
+++ b/llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
@@ -1,4 +1,5 @@
# RUN: llc %s -o - -run-pass=machine-sink -mtriple=x86_64-- | FileCheck %s
+# RUN: llc %s -o - -passes=machine-sink -mtriple=x86_64-- | FileCheck %s
# This is a copy of test/CodeGen/X86/MachineSink-DbgValue.ll, where we
# additionally test that when the MOV32rm defining %0 is sunk, it leaves
# an 'undef' DBG_VALUE behind to terminate earlier location ranges.
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