[llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)

[via llvm-commits]

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@@ -11766,9 +11771,13 @@ SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
   SDValue BasePtr = LN->getBasePtr();
   EVT VT = Op.getValueType();
 
-  if (VT != MVT::v256i1 && VT != MVT::v512i1)
+  if (VT != MVT::v256i1 && VT != MVT::v512i1 && VT != MVT::v1024i1)
     return Op;
 
+  // Used for dense math registers.
+  assert((VT != MVT::v1024i1 || Subtarget.isISAFuture()) &&
+         "Type unsupported for this processor");
+
   // Type v256i1 is used for pairs and v512i1 is used for accumulators.
   // Here we create 2 or 4 v16i8 loads to load the pair or accumulator value in
   // 2 or 4 vsx registers.
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RolandF77 wrote:

Code removed.

https://github.com/llvm/llvm-project/pull/126969