[llvm] [PowerPC] custom lower v1024i1 load/store (PR #126969)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 21 12:07:14 PST 2025
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@@ -11832,20 +11873,43 @@ SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
MachineSDNode *ExtNode = DAG.getMachineNode(
PPC::DMXXEXTFDMR512, dl, ReturnTypes, Op.getOperand(1));
- Value = SDValue(ExtNode, 0);
- Value2 = SDValue(ExtNode, 1);
+ ValueVec.push_back(SDValue(ExtNode, 0));
+ ValueVec.push_back(SDValue(ExtNode, 1));
} else
Value = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, Value);
NumVecs = 4;
+
+ } else if (StoreVT == MVT::v1024i1) {
+ SDValue Lo(DAG.getMachineNode(
+ TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
+ Op.getOperand(1),
+ DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32)),
+ 0);
+ SDValue Hi(DAG.getMachineNode(
+ TargetOpcode::EXTRACT_SUBREG, dl, MVT::v512i1,
+ Op.getOperand(1),
+ DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32)),
+ 0);
+ EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1};
+ MachineSDNode *ExtNode =
+ DAG.getMachineNode(PPC::DMXXEXTFDMR512, dl, ReturnTypes, Lo);
+ ValueVec.push_back(SDValue(ExtNode, 0));
+ ValueVec.push_back(SDValue(ExtNode, 1));
+ ExtNode = DAG.getMachineNode(PPC::DMXXEXTFDMR512_HI, dl, ReturnTypes, Hi);
+ ValueVec.push_back(SDValue(ExtNode, 0));
+ ValueVec.push_back(SDValue(ExtNode, 1));
+ NumVecs = 8;
}
for (unsigned Idx = 0; Idx < NumVecs; ++Idx) {
unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx;
SDValue Elt;
if (Subtarget.isISAFuture()) {
VecNum = Subtarget.isLittleEndian() ? 1 - (Idx % 2) : (Idx % 2);
- Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8,
- Idx > 1 ? Value2 : Value,
- DAG.getConstant(VecNum, dl, getPointerTy(DAG.getDataLayout())));
+ unsigned Pairx =
+ Subtarget.isLittleEndian() ? (NumVecs - Idx - 1) / 2 : Idx / 2;
----------------
RolandF77 wrote:
Code removed.
https://github.com/llvm/llvm-project/pull/126969
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