[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

Hi @paulwalker-arm, thanks again for your feedback. I should have addressed most of it now.

I'm still keen to try the route you suggested via AArch64LoadStoreOpt once #127837 gets sorted (assuming you still think that's the preferable approach).

Please let me know if you have any other comments or suggestions.

https://github.com/llvm/llvm-project/pull/127500