[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -aarch64-sve-vector-bits-max=0   < %s | FileCheck %s --check-prefix=CHECK-VLA
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rj-jesus wrote:

Thanks, I was initially planning to use it to check the general SVE folds to LDR/STR, but you're right, there's already enough coverage for those. I've removed the `-aarch64-sve-vector-bits-max=0` RUN line and cleaned up the tests a bit.

https://github.com/llvm/llvm-project/pull/127500