[llvm] AMDGPU: Restrict src0 to VGPRs only for certain cvt scale opcodes. (PR #127464)

[Pravin Jagtap via llvm-commits]

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@@ -1818,6 +1818,18 @@ class getVOP3VRegSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
          1                 : RegisterOperand<VGPR_32>);
 }
 
+// VGPR only VOP3 src with 9 bit encoding
+class getVOP3VSrcReg9ForVT<ValueType VT> {
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pravinjagtap wrote:

Its because https://github.com/llvm/llvm-project/blob/0948fc85aa99a8fd193d2d66a517e31b8b639f20/llvm/lib/Target/AMDGPU/VOP2Instructions.td#L426C18-L426C37 is different downstream. Downstream uses `getVOP3VRegForVT` over `getVOP3VRegSrcForVT`

https://github.com/llvm/llvm-project/pull/127464