[llvm] [RISCV] [MachineOutliner] Analyze all candidates (PR #127659)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -3047,35 +3042,32 @@ RISCVInstrInfo::getOutliningCandidateInfo(
     std::vector<outliner::Candidate> &RepeatedSequenceLocs,
     unsigned MinRepeats) const {
 
-  // Each RepeatedSequenceLoc is identical.
-  outliner::Candidate &Candidate = RepeatedSequenceLocs[0];
-  auto CandidateInfo = analyzeCandidate(Candidate);
-  if (!CandidateInfo)
-    RepeatedSequenceLocs.clear();
+  // Analyze each candidate and erase the ones that are not viable.
+  llvm::erase_if(RepeatedSequenceLocs, analyzeCandidate);
 
   // If the sequence doesn't have enough candidates left, then we're done.
   if (RepeatedSequenceLocs.size() < MinRepeats)
     return std::nullopt;
 
+  // Each RepeatedSequenceLoc is identical.
+  outliner::Candidate &Candidate = RepeatedSequenceLocs[0];
   unsigned InstrSizeCExt =
       Candidate.getMF()->getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 2
                                                                           : 4;
----------------
svs-quic wrote:

> I don't know how we end up constructing a subtarget for the outlined function, based off the candidates.

There is a target hook `mergeOutliningCandidateAttributes`, the default implementation of which just picks the first candidate and copies over all the target features to the outlined function.

```
// Include target features from an arbitrary candidate for the outlined
// function. This makes sure the outlined function knows what kinds of
// instructions are going into it. This is fine, since all parent functions
// must necessarily support the instructions that are in the outlined region.
outliner::Candidate &FirstCand = Candidates.front();
const Function &ParentFn = FirstCand.getMF()->getFunction();
if (ParentFn.hasFnAttribute("target-features"))
  F.addFnAttr(ParentFn.getFnAttribute("target-features"));
if (ParentFn.hasFnAttribute("target-cpu"))
  F.addFnAttr(ParentFn.getFnAttribute("target-cpu"));
```

We could maybe override that for RISCV and not pass the Zca/C flag if one of the candidates does not have it set in a follow-up patch?


https://github.com/llvm/llvm-project/pull/127659