[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[Aiden Grossman via llvm-commits]

boomanaiden154 wrote:

> I believe it is a warning - it still produces results when I've tried it in the past.

It's a warning, but definitely one that should be fixed. Leaving whatever values were "live-in" to the registers upon starting the benchmark can cause a lot of problems depending upon the instructions being benchmarked. Having consistent values can be very important for benchmark reproducibility. Not familiar enough with value dependent variable latency instructions on ARM to say whether or not it would matter here, but good to fix it regardless.

https://github.com/llvm/llvm-project/pull/127564