[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)
Aiden Grossman via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 00:42:53 PST 2025
================
@@ -35,6 +35,48 @@ static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
.addImm(Value.getZExtValue());
}
+static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+ const APInt &Value) {
+ if (Value.getBitWidth() > RegBitWidth)
+ llvm_unreachable("Value must fit in the ZPR Register");
+ // For ZPR, we typically use DUPM instruction to load immediate values
+ return MCInstBuilder(AArch64::DUPM_ZI)
+ .addReg(Reg)
+ .addImm(Value.getZExtValue());
+}
+
+static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+ const APInt &Value) {
+ if (Value.getBitWidth() > RegBitWidth)
+ llvm_unreachable("Value must fit in the PPR Register");
----------------
boomanaiden154 wrote:
```suggestion
assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register");
```
https://github.com/llvm/llvm-project/pull/127564
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