[llvm] [AMDGPU] - Fix non-deterministic compile issue (PR #126271)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: David Stuttard (dstutt)

<details>
<summary>Changes</summary>

4ce1f9079d4d3 [AMDGPU] Allow rematerialization of instructions with virtual register uses (#<!-- -->124327)
made changes that require an ordered traversal of a DenseMap. Changing it to MapVector which
respects insertion order.


---
Full diff: https://github.com/llvm/llvm-project/pull/126271.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/GCNSchedStrategy.h (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
index 7d3e63df43da60..e3da8d30056293 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
@@ -442,7 +442,7 @@ class PreRARematStage : public GCNSchedStage {
 
   // Map a trivially rematerializable def to a list of regions at MinOccupancy
   // that has the defined reg as a live-in.
-  DenseMap<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
+  MapVector<MachineInstr *, SmallVector<unsigned, 4>> RematDefToLiveInRegions;
 
   // Collect all trivially rematerializable VGPR instructions with a single def
   // and single use outside the defining block into RematerializableInsts.

``````````

</details>


https://github.com/llvm/llvm-project/pull/126271