[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -11890,6 +11891,61 @@ SDValue TargetLowering::expandVECTOR_COMPRESS(SDNode *Node,
   return DAG.getLoad(VecVT, DL, Chain, StackPtr, PtrInfo);
 }
 
+SDValue TargetLowering::expandPartialReduceMLA(SDNode *N,
+                                               SelectionDAG &DAG) const {
+  SDLoc DL(N);
+  SDValue Acc = N->getOperand(0);
+  SDValue MulLHS = N->getOperand(1);
+  SDValue MulRHS = N->getOperand(2);
+  EVT ReducedTy = Acc.getValueType();
+  EVT FullTy = MulLHS.getValueType();
+
+  auto ExtendToAccEltVT = [&](SDValue V) {
+    unsigned ExtOpc = V->getOpcode() == ISD::SIGN_EXTEND ? ISD::SIGN_EXTEND
+                                                         : ISD::ZERO_EXTEND;
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paulwalker-arm wrote:

The opcodes of the multiply operands are not relevant.  All that matters is `N`'s opcode.  If it's `PARTIAL_REDUCE_SMLA` then promoted multiply operands should be signed extended otherwise they should be zero extended.

https://github.com/llvm/llvm-project/pull/125207