[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,154 @@
+//===- RISCVVMV0Elimination.cpp - VMV0 Elimination -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// Mask operands in vector pseudos have to be in v0. We select them as a virtual
+// register in the singleton vmv0 register class instead of copying them to $v0
+// straight away, to make optimizing masks easier.
+//
+// However the register allocator struggles with singleton register classes and
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lukel97 wrote:

Off the top of my head the reason why we were ending up with instructions with two separate uses of vmv0 was because copies were getting coalesced into the vmv0 class. There shouldn't be any instructions with two vmv0 operands.

It might be worth trying to change this pass to inflate any unnecessary vmv0 register classes so we avoid this situation? Ideally in a separate PR so we minimise the test diff from isel's current behaviour

https://github.com/llvm/llvm-project/pull/125026