[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,154 @@
+//===- RISCVVMV0Elimination.cpp - VMV0 Elimination -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// Mask operands in vector pseudos have to be in v0. We select them as a virtual
+// register in the singleton vmv0 register class instead of copying them to $v0
+// straight away, to make optimizing masks easier.
+//
+// However the register allocator struggles with singleton register classes and
----------------
arsenm wrote:

The problem is if you have more than 1 value that need to be live at the same point, as in instruction.

```
  %0:my_rc = DEF0
  %1:my_rc = DEF1
  SOME_INST implicit %0, implicit %1
```
Is the kind of case that will fail. Other cases where they don't need to be live at the same point should work 


https://github.com/llvm/llvm-project/pull/125026