[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)
James Chesterman via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 03:22:08 PST 2025
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@@ -1451,6 +1451,19 @@ enum NodeType {
VECREDUCE_UMAX,
VECREDUCE_UMIN,
+ // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+ // Input1 and Input2 are multiplied together. This result is concatenated to
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JamesChesterman wrote:
Done
https://github.com/llvm/llvm-project/pull/125207
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