[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[James Chesterman via llvm-commits]

================
@@ -7883,6 +7854,30 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
 
     break;
   }
+  case ISD::PARTIAL_REDUCE_UMLA:
+  case ISD::PARTIAL_REDUCE_SMLA: {
+    EVT AccVT = N1.getValueType();
+    EVT Input1VT = N2.getValueType();
+    EVT Input2VT = N3.getValueType();
+    assert(Input1VT == Input2VT &&
----------------
JamesChesterman wrote:

Done (used `isVector()`).

https://github.com/llvm/llvm-project/pull/125207