[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

================
@@ -1451,6 +1451,19 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // Input1 and Input2 are multiplied together. This result is concatenated to
----------------
paulwalker-arm wrote:

Looks like you've accidentally chopped the "The partial reduction nodes sign or zero extend.." which is also key to the operation.

https://github.com/llvm/llvm-project/pull/125207