[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Piyou Chen via llvm-commits]

================
@@ -954,3 +954,36 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 
   return BaseImplRetVal;
 }
+
+bool RISCVRegisterInfo::needReleasePendingQueue(
+    MachineFunction &MF, ArrayRef<unsigned> MaxSetPressure) const {
+  for (unsigned Idx = 0; Idx < MaxSetPressure.size(); Idx++) {
+    // Consider only the RVV Register, as RVV spilling/reloading has higher
+    // potential costs than hazards.
+    if (!StringRef(getRegPressureSetName(Idx)).starts_with("VM") &&
+        !StringRef(getRegPressureSetName(Idx)).starts_with("VRM8NoV0"))
----------------
BeMg wrote:

How can we find the latest vector register pressure sets if 'VM' and 'VRM8NoV0' change when adding new register classes?

Are you suggesting using a static helper function like this:
```
static bool isVectorRegPSet(StringRef s) {
     std::vector<StringRef> TargetPset = {"VM", "VRM8NoV0"}; // Or 11 and 13 for PSet Idx

     return llvm::find_if(TargetPset, s) != TargetPsetName.end();
}
```

and update the `TargetPset` when adding new register classes?

https://github.com/llvm/llvm-project/pull/125468