[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Jianjian Guan via llvm-commits]

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@@ -954,3 +954,36 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 
   return BaseImplRetVal;
 }
+
+bool RISCVRegisterInfo::needReleasePendingQueue(
+    MachineFunction &MF, ArrayRef<unsigned> MaxSetPressure) const {
+  for (unsigned Idx = 0; Idx < MaxSetPressure.size(); Idx++) {
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jacquesguan wrote:

Early exit when we don't have any vector extensions?

https://github.com/llvm/llvm-project/pull/125468