[llvm] [AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC (PR #125614)

[Craig Topper via llvm-commits]

topperc wrote:

> Note that this makes the vector case less constrained (and inconsistent with REV32/REV64, which are vector-only). I think it would be better to introduce a new enum value for the scalar case. Is is only used in [one](https://github.com/llvm/llvm-project/blob/8017ca1d0056907331ff7542ac9ff1ff5ec969a2/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L22497) place.

Does that constraint on vector provide any value? Conceptually its the same operation, rev16 on elements if you consider scalar to be a single element. It's like ISD::BSWAP but operating on 16 bits instead of bytes. I can change all of them to use SDTIntUnaryOp.

https://github.com/llvm/llvm-project/pull/125614