[llvm] [AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC (PR #125614)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 3 18:06:30 PST 2025
s-barannikov wrote:
Note that this makes the vector case less constrained (and inconsistent with REV32/REV64, which are vector-only). I think it would be better to introduce a new enum value for the scalar case.
Is is only used in [one](https://github.com/llvm/llvm-project/blob/8017ca1d0056907331ff7542ac9ff1ff5ec969a2/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L22497) place.
https://github.com/llvm/llvm-project/pull/125614
More information about the llvm-commits
mailing list