[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,154 @@
+//===- RISCVVMV0Elimination.cpp - VMV0 Elimination -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// Mask operands in vector pseudos have to be in v0. We select them as a virtual
+// register in the singleton vmv0 register class instead of copying them to $v0
+// straight away, to make optimizing masks easier.
+//
+// However the register allocator struggles with singleton register classes and
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lukel97 wrote:

> I've never really understood why 3 virtual registers with overlapping live ranges in a 2 element register class is fine, but 2 overlapping virtual registers in a 1 element register class isn't.

Maybe this is just a limitation of how GreedyRegAlloc implements spilling, i.e. it requires at least two registers in a class?

One way to think of RISCVVMV0Elimination is that it "spills" vmv0 register classes to vr register classes by inserting copies and inflating the register class. That way we're removing any overlapping live ranges. 

https://github.com/llvm/llvm-project/pull/125026