[llvm] [RISCV] Simplify usage of SplatPat_simm5_plus1. NFC (PR #125340)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 1 00:20:28 PST 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/125340
Make SplatPat_simm5_plus1 responsible for decrementing the immediate instead of requiring DecImm SDNodeXForm to be used after. This allows better sharing of tablegen classes.
>From ed4c019073e19d154466e3cad7799698e058989e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 1 Feb 2025 00:18:32 -0800
Subject: [PATCH] [RISCV] Simplify usage of SplatPat_simm5_plus1. NFC
Make SplatPat_simm5_plus1 responsible for decrementing the immediate
instead of requires DecImm SDNodeXForm to be used after. This allows
better sharing of tablegen classes.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 11 +++--
.../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 41 +++++-----------
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 48 +++++--------------
3 files changed, 31 insertions(+), 69 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9855028ead9e20..8ac80cb64f93c8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3538,7 +3538,8 @@ bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
- std::function<bool(int64_t)> ValidateImm) {
+ std::function<bool(int64_t)> ValidateImm,
+ bool Decrement = false) {
SDValue Splat = findVSplat(N);
if (!Splat || !isa<ConstantSDNode>(Splat.getOperand(1)))
return false;
@@ -3561,6 +3562,9 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
if (!ValidateImm(SplatImm))
return false;
+ if (Decrement)
+ SplatImm -= 1;
+
SplatVal =
DAG.getSignedTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
return true;
@@ -3574,7 +3578,8 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget,
- [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; });
+ [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
+ /*Decrement=*/true);
}
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
@@ -3582,7 +3587,7 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
return selectVSplatImmHelper(
N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) {
return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
- });
+ }, /*Decrement=*/true);
}
bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 880ea0ae0a976c..8f77b2ce34d1f1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -313,29 +313,10 @@ multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
SplatPat, GPR>;
multiclass VPatIntegerSetCCSDNode_VI_Swappable<string instruction_name,
- CondCode cc, CondCode invcc>
+ CondCode cc, CondCode invcc,
+ ComplexPattern splatpat_kind = SplatPat_simm5>
: VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VI",
- SplatPat_simm5, simm5>;
-
-multiclass VPatIntegerSetCCSDNode_VIPlus1_Swappable<string instruction_name,
- CondCode cc, CondCode invcc,
- ComplexPattern splatpat_kind> {
- foreach vti = AllIntegerVectors in {
- defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
- let Predicates = GetVTypePredicates<vti>.Predicates in {
- def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
- (vti.Vector (splatpat_kind simm5:$rs2)),
- cc)),
- (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
- vti.AVL, vti.Log2SEW)>;
- def : Pat<(vti.Mask (setcc (vti.Vector (splatpat_kind simm5:$rs2)),
- (vti.Vector vti.RegClass:$rs1),
- invcc)),
- (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
- vti.AVL, vti.Log2SEW)>;
- }
- }
-}
+ splatpat_kind, simm5>;
multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
string inst_name,
@@ -1021,14 +1002,14 @@ defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
-defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
- SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
- SplatPat_simm5_plus1_nonzero>;
-defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE,
- SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
- SplatPat_simm5_plus1_nonzero>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLT, SETGT,
+ SplatPat_simm5_plus1>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
+ SplatPat_simm5_plus1_nonzero>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGE, SETLE,
+ SplatPat_simm5_plus1>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
+ SplatPat_simm5_plus1_nonzero>;
// 11.9. Vector Integer Min/Max Instructions
defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 2026ba79e623d8..f35dc6eb2cb8be 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1052,32 +1052,8 @@ multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_nam
}
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
- CondCode cc, CondCode invcc> {
- defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
- (SplatPat_simm5 simm5:$rs2), cc,
- VR:$passthru,
- (vti.Mask V0),
- VLOpFrag)),
- (instruction_masked VR:$passthru, vti.RegClass:$rs1,
- XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
- vti.Log2SEW)>;
-
- // FIXME: Can do some canonicalization to remove these patterns.
- def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
- (vti.Vector vti.RegClass:$rs1), invcc,
- VR:$passthru,
- (vti.Mask V0),
- VLOpFrag)),
- (instruction_masked VR:$passthru, vti.RegClass:$rs1,
- simm5:$rs2, (vti.Mask V0), GPR:$vl,
- vti.Log2SEW)>;
-}
-
-multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
- string instruction_name,
- CondCode cc, CondCode invcc,
- ComplexPattern splatpat_kind> {
+ CondCode cc, CondCode invcc,
+ ComplexPattern splatpat_kind = SplatPat_simm5> {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc,
@@ -1085,7 +1061,7 @@ multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
- (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
+ XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
// FIXME: Can do some canonicalization to remove these patterns.
@@ -1095,7 +1071,7 @@ multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
- (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
+ simm5:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
}
@@ -2173,14 +2149,14 @@ foreach vti = AllIntegerVectors in {
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
- defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
- SplatPat_simm5_plus1>;
- defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
- SplatPat_simm5_plus1_nonzero>;
- defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
- SplatPat_simm5_plus1>;
- defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
- SplatPat_simm5_plus1_nonzero>;
+ defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
+ SplatPat_simm5_plus1>;
+ defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
+ SplatPat_simm5_plus1_nonzero>;
+ defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
+ SplatPat_simm5_plus1>;
+ defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
+ SplatPat_simm5_plus1_nonzero>;
}
} // foreach vti = AllIntegerVectors
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