[llvm] [AMDGPU] Allow rematerialization of instructions with virtual register uses (PR #124327)

[Jeffrey Byrnes via llvm-commits]

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@@ -1615,6 +1615,61 @@ void GCNSchedStage::revertScheduling() {
   DAG.Regions[RegionIdx] = std::pair(DAG.RegionBegin, DAG.RegionEnd);
 }
 
+bool PreRARematStage::allUsesAvailableAt(const MachineInstr *InstToRemat,
+                                         SlotIndex OriginalIdx,
+                                         SlotIndex RematIdx) const {
+
+  LiveIntervals *LIS = DAG.LIS;
+  MachineRegisterInfo &MRI = DAG.MRI;
+  OriginalIdx = OriginalIdx.getRegSlot(true);
+  RematIdx = std::max(RematIdx, RematIdx.getRegSlot(true));
+  for (const MachineOperand &MO : InstToRemat->operands()) {
+    if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
+      continue;
+
+    // Do not attempt to reason about PhysRegs
+    if (!MO.getReg().isVirtual()) {
+      assert(DAG.MRI.isConstantPhysReg(MO.getReg()) ||
+             DAG.TII->isIgnorableUse(MO));
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jrbyrnes wrote:

> This can be m0 or flat_scr for example.

I think this would be covered by `DAG.MRI.isConstantPhysReg(MO.getReg()` ?

https://github.com/llvm/llvm-project/pull/124327