[llvm] SCEV: teach isImpliedViaOperations about samesign (PR #124270)

[Ramkumar Ramachandra via llvm-commits]

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@@ -11882,22 +11880,23 @@ bool ScalarEvolution::isImpliedCondBalancedTypes(
     // Forms 1. and 2. require swapping the operands of one condition. Don't
     // do this if it would break canonical constant/addrec ordering.
     if (!isa<SCEVConstant>(RHS) && !isa<SCEVAddRecExpr>(LHS))
-      return isImpliedCondOperands(FoundPred, RHS, LHS, FoundLHS, FoundRHS,
-                                   CtxI);
+      return isImpliedCondOperands(ICmpInst::getSwappedCmpPredicate(*P), RHS,
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artagnon wrote:

Wouldn't that result in a correctness issue?

https://github.com/llvm/llvm-project/pull/124270