[llvm] clastb representation in existing IR, and AArch64 codegen (PR #112738)

[Sander de Smalen via llvm-commits]

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@@ -19944,6 +19945,28 @@ performLastTrueTestVectorCombine(SDNode *N,
   return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE);
 }
 
+static SDValue
+performExtractLastActiveCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
+                                const AArch64Subtarget *Subtarget) {
+  assert(N->getOpcode() == ISD::EXTRACT_VECTOR_ELT);
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue Vec = N->getOperand(0);
+  SDValue Idx = N->getOperand(1);
+
+  if (!Subtarget->hasSVE() || DCI.isBeforeLegalize() ||
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sdesmalen-arm wrote:

nit: the test for `Subtarget->hasSVE()` is redundant and tested by the `getOperationAction(..) == legal` below.

https://github.com/llvm/llvm-project/pull/112738