[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Sander de Smalen via llvm-commits]

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@@ -2824,6 +2833,12 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
   return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
+  SDValue Res = DAG.expandPartialReduceMLA(N);
+  ReplaceValueWith(SDValue(N, 0), Res);
+  return SDValue();
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sdesmalen-arm wrote:

This code should just promote the operands to a legal type.

This will however mean that if all types are legal, that the target will not be able to select the operation. This you can fix by marking the operations as `Expand` for AArch64, and calling the expand code from `LegalizeVectorOps`. Any sign/zero-extension of the operands by the expand code, will then be revisited by a second type-legalization stage.

https://github.com/llvm/llvm-project/pull/125207