[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Sander de Smalen via llvm-commits]

================
@@ -1451,6 +1451,20 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_*MLA (Accumulator, Input1, Input2)
+  // Partial reduction nodes. Input1 and Input2 are multiplied together before
+  // being reduced, by addition to the number of elements that Accumulator's
+  // type has.
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sdesmalen-arm wrote:

```suggestion
  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
  // The partial reduction nodes sign-or zero extend Input1 and Input2 to
  // the element type of Accumulator before multiplying their results.
  // The multiplied result is then reduced using addition to the result
  // type of Accumulator. The result is added to Accumulator and returned.
```

https://github.com/llvm/llvm-project/pull/125207