[llvm] [AMDGPU] Stop adding implicit def of superreg in copyPhysReg (PR #125255)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 31 09:11:45 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
Previously when copyPhysReg expanded a COPY into multiple MOV
instructions it added an implicit def of the destination superreg to the
first MOV. Removing these does not cause any liveness verification
problems and still passes Vulkan CTS for correctness testing.
---
Patch is 1.89 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/125255.diff
222 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+18-35)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll (+48-46)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll (+84-80)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/bitcast_38_i16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll (+21-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll (+86-80)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll (+38-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll (+281-281)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll (+12-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll (+39-37)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll (+4-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll (+12-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+43-43)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll (+22-21)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+43-43)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/subo.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/widen-i8-i16-scalar-loads.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll (+24-27)
- (modified) llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir (+87-87)
- (modified) llvm/test/CodeGen/AMDGPU/add.ll (+19-15)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll (+51-51)
- (modified) llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/bitreverse.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll (+87-91)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll (+70-78)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll (+70-78)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/build_vector.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/call-argument-types.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/carryout-selection.ll (+28-24)
- (modified) llvm/test/CodeGen/AMDGPU/cluster_stores.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf.ll (+7-4)
- (modified) llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/copy-phys-reg-implicit-operand-kills-subregs.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir (+68-68)
- (modified) llvm/test/CodeGen/AMDGPU/ctlz.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/ctpop64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/cttz.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/ds_read2.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/fabs.f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fabs.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll (+13-13)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/flat-scratch.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll (+214-214)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll (+66-66)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll (+108-108)
- (modified) llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll (+99-99)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/fnearbyint.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.f64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fabs.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/fp-classify.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/frem.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/fshl.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/fshr.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/global-saddr-load.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll (+56-56)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll (+45-45)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll (+140-140)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll (+104-104)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll (+104-104)
- (modified) llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll (+140-140)
- (modified) llvm/test/CodeGen/AMDGPU/half.ll (+108-106)
- (modified) llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll (+44-42)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+25-23)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/itofp.i128.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/kernel-args.ll (+42-41)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll (+64-64)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll (+51-51)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.simple.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll (+31-31)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll (+45-43)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll (+48-48)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll (+25-25)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.pops.exiting.wave.id.ll (+44-24)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx11.ll (+40-44)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.gfx12.ll (+20-28)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll (+78-36)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll (+49-49)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-f64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+224-222)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i16.ll (+232-232)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i32.ll (+145-140)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i64.ll (+35-34)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i8.ll (+287-287)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i16.ll (+136-135)
- (modified) llvm/test/CodeGen/AMDGPU/load-global-i32.ll (+87-88)
- (modified) llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+5-3)
- (modified) llvm/test/CodeGen/AMDGPU/max-hard-clause-length.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/memcpy-crash-issue63986.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/memmove-var-size.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/memory_clause.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/min.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/or.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll (+3-2)
- (modified) llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/rem_i128.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/rotl.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/rotr.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/saddo.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/sdiv64.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll (+20-20)
- (modified) llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll (+39-40)
- (modified) llvm/test/CodeGen/AMDGPU/srem.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/srem64.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/store-local.128.ll (+9-10)
- (modified) llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/sub.ll (+5-4)
- (modified) llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/swdev380865.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/trap-abis.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/trunc-store.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/uaddo.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/udiv64.ll (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/udivrem.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll (+14-14)
- (modified) llvm/test/CodeGen/AMDGPU/urem64.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/usubo.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/v_cndmask.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/wave32.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/wqm.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/xor.ll (+6-6)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 35667801c809d5..116bb09de0f99f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -627,13 +627,11 @@ static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
/// Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. It is not
/// possible to have a direct copy in these cases on GFX908, so an intermediate
/// VGPR copy is required.
-static void indirectCopyToAGPR(const SIInstrInfo &TII,
- MachineBasicBlock &MBB,
+static void indirectCopyToAGPR(const SIInstrInfo &TII, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc,
RegScavenger &RS, bool RegsOverlap,
- Register ImpDefSuperReg = Register(),
Register ImpUseSuperReg = Register()) {
assert((TII.getSubtarget().hasMAIInsts() &&
!TII.getSubtarget().hasGFX90AInsts()) &&
@@ -681,10 +679,9 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII,
}
MachineInstrBuilder Builder =
- BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
- .add(DefOp);
- if (ImpDefSuperReg)
- Builder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64),
+ DestReg)
+ .add(DefOp);
if (ImpUseSuperReg) {
Builder.addReg(ImpUseSuperReg,
@@ -738,12 +735,8 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII,
getKillRegState(KillSrc) | RegState::Implicit);
}
- MachineInstrBuilder DefBuilder
- = BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
- .addReg(Tmp, RegState::Kill);
-
- if (ImpDefSuperReg)
- DefBuilder.addReg(ImpDefSuperReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, TII.get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), DestReg)
+ .addReg(Tmp, RegState::Kill);
}
static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
@@ -791,9 +784,6 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
if (!Forward)
std::swap(FirstMI, LastMI);
- FirstMI->addOperand(
- MachineOperand::CreateReg(DestReg, true /*IsDef*/, true /*IsImp*/));
-
if (KillSrc)
LastMI->addRegisterKilled(SrcReg, &RI);
}
@@ -1118,34 +1108,27 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx);
assert(DestSubReg && SrcSubReg && "Failed to find subregs!");
- bool IsFirstSubreg = Idx == 0;
bool UseKill = CanKillSuperReg && Idx == SubIndices.size() - 1;
if (Opcode == AMDGPU::INSTRUCTION_LIST_END) {
- Register ImpDefSuper = IsFirstSubreg ? Register(DestReg) : Register();
Register ImpUseSuper = SrcReg;
indirectCopyToAGPR(*this, MBB, MI, DL, DestSubReg, SrcSubReg, UseKill,
- *RS, Overlap, ImpDefSuper, ImpUseSuper);
+ *RS, Overlap, ImpUseSuper);
} else if (Opcode == AMDGPU::V_PK_MOV_B32) {
- MachineInstrBuilder MIB =
- BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
- .addImm(SISrcMods::OP_SEL_1)
- .addReg(SrcSubReg)
- .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
- .addReg(SrcSubReg)
- .addImm(0) // op_sel_lo
- .addImm(0) // op_sel_hi
- .addImm(0) // neg_lo
- .addImm(0) // neg_hi
- .addImm(0) // clamp
- .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
- if (IsFirstSubreg)
- MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
+ BuildMI(MBB, MI, DL, get(AMDGPU::V_PK_MOV_B32), DestSubReg)
+ .addImm(SISrcMods::OP_SEL_1)
+ .addReg(SrcSubReg)
+ .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1)
+ .addReg(SrcSubReg)
+ .addImm(0) // op_sel_lo
+ .addImm(0) // op_sel_hi
+ .addImm(0) // neg_lo
+ .addImm(0) // neg_hi
+ .addImm(0) // clamp
+ .addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
} else {
MachineInstrBuilder Builder =
BuildMI(MBB, MI, DL, get(Opcode), DestSubReg).addReg(SrcSubReg);
- if (IsFirstSubreg)
- Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
index ff5880819020da..99daa0e99b8c99 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
@@ -679,8 +679,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX7-LABEL: s_saddo_i64:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_add_u32 s4, s0, s2
-; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: s_addc_u32 s5, s1, s3
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX7-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -696,8 +696,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX8-LABEL: s_saddo_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_u32 s4, s0, s2
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_addc_u32 s5, s1, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
@@ -713,8 +713,8 @@ define amdgpu_ps i64 @s_saddo_i64(i64 inreg %a, i64 inreg %b) {
; GFX9-LABEL: s_saddo_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 s4, s0, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_addc_u32 s5, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
index 28ed88f4cf8fb8..f48a4823a6d18a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s
; RUN: llc -global-isel -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
@@ -96,8 +96,8 @@ define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -192,8 +192,8 @@ define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -294,8 +294,8 @@ define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_xor_b32_e32 v4, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -392,8 +392,8 @@ define amdgpu_cs void @atomic_ptr_add_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_add_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -492,8 +492,8 @@ define amdgpu_cs void @atomic_ptr_sub_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
@@ -598,8 +598,8 @@ define amdgpu_cs void @atomic_ptr_xor_and_format(ptr addrspace(8) inreg %arg) {
; GCN-NEXT: v_readfirstlane_b32 s4, v1
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: v_xor_b32_e32 v4, s4, v0
-; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
index 424388a30e99b4..b60b20f1f0aefb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll
@@ -1811,9 +1811,9 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[9:10], v[9:10]
; GFX12-NEXT: v_max_num_f64_e32 v[7:8], v[0:1], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX12-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v6, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -1852,9 +1852,9 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX11-NEXT: v_max_f64 v[7:8], v[0:1], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX11-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v6, s[0:3], 0 offen glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1904,10 +1904,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX908-NEXT: v_mov_b32_e32 v9, v0
; GFX908-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX908-NEXT: v_max_f64 v[7:8], v[0:1], v[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v7
-; GFX908-NEXT: v_mov_b32_e32 v1, v8
; GFX908-NEXT: v_mov_b32_e32 v2, v9
; GFX908-NEXT: v_mov_b32_e32 v3, v10
+; GFX908-NEXT: v_mov_b32_e32 v0, v7
+; GFX908-NEXT: v_mov_b32_e32 v1, v8
; GFX908-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v6, s[16:19], 0 offen glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
@@ -1935,10 +1935,10 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_
; GFX8-NEXT: v_mov_b32_e32 v9, v0
; GFX8-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX8-NEXT: v_max_f64 v[7:8], v[0:1], v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v7
-; GFX8-NEXT: v_mov_b32_e32 v1, v8
; GFX8-NEXT: v_mov_b32_e32 v2, v9
; GFX8-NEXT: v_mov_b32_e32 v3, v10
+; GFX8-NEXT: v_mov_b32_e32 v0, v7
+; GFX8-NEXT: v_mov_b32_e32 v1, v8
; GFX8-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v6, s[16:19], 0 offen glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
index b52a39f1a55c8f..ebbd7856826292 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll
@@ -1811,9 +1811,9 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[9:10], v[9:10]
; GFX12-NEXT: v_min_num_f64_e32 v[7:8], v[0:1], v[4:5]
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX12-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX12-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v6, s[0:3], null offen th:TH_ATOMIC_RETURN
; GFX12-NEXT: s_wait_loadcnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_DEV
@@ -1852,9 +1852,9 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX11-NEXT: v_min_f64 v[7:8], v[0:1], v[4:5]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX11-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8
; GFX11-NEXT: buffer_atomic_cmpswap_b64 v[0:3], v6, s[0:3], 0 offen glc
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
@@ -1904,10 +1904,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX908-NEXT: v_mov_b32_e32 v9, v0
; GFX908-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX908-NEXT: v_min_f64 v[7:8], v[0:1], v[4:5]
-; GFX908-NEXT: v_mov_b32_e32 v0, v7
-; GFX908-NEXT: v_mov_b32_e32 v1, v8
; GFX908-NEXT: v_mov_b32_e32 v2, v9
; GFX908-NEXT: v_mov_b32_e32 v3, v10
+; GFX908-NEXT: v_mov_b32_e32 v0, v7
+; GFX908-NEXT: v_mov_b32_e32 v1, v8
; GFX908-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v6, s[16:19], 0 offen glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: buffer_wbinvl1
@@ -1935,10 +1935,10 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_
; GFX8-NEXT: v_mov_b32_e32 v9, v0
; GFX8-NEXT: v_max_f64 v[0:1], v[9:10], v[9:10]
; GFX8-NEXT: v_min_f64 v[7:8], v[0:1], v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v0, v7
-; GFX8-NEXT: v_mov_b32_e32 v1, v8
; GFX8-NEXT: v_mov_b32_e32 v2, v9
; GFX8-NEXT: v_mov_b32_e32 v3, v10
+; GFX8-NEXT: v_mov_b32_e32 v0, v7
+; GFX8-NEXT: v_mov_b32_e32 v1, v8
; GFX8-NEXT: buffer_atomic_cmpswap_x2 v[0:3], v6, s[16:19], 0 offen glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
index b96fc71be057e7..012bcfc88368e5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
@@ -1025,14 +1025,14 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(ptr %out, ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_ret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_dec_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX11-NEXT: flat_store_b32 v[0:1], v2
; GFX11-NEXT: s_endpgm
%gep = getelementptr i32, ptr %ptr, i32 4
@@ -1112,14 +1112,14 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_system(ptr %out, ptr %
; GFX11-LABEL: flat_atomic_dec_ret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: flat_atomic_dec_u32 v2, v[0:1], v2 offset:16 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX11-NEXT: flat_store_b32 v[0:1], v2
; GFX11-NEXT: s_endpgm
%gep = getelementptr i32, ptr %ptr, i32 4
@@ -1255,9 +1255,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(ptr %ptr) #1 {
; GFX11-LABEL: flat_atomic_dec_noret_i32_offset:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_dec_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1329,9 +1329,9 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_system(ptr %ptr) #1
; GFX11-LABEL: flat_atomic_dec_noret_i32_offset_system:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v2, 42
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, 42 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: flat_atomic_dec_u32 v[0:1], v2 offset:16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1435,18 +1435,18 @@ define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(ptr %out, ptr %
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
; GFX11-NEXT: v_dual_mov_b32 v3, 42 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_lshlrev_b32 v2, 2, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX11-NEXT: flat_atomic_dec_u32 v3, v[0:1], v3 offset:20 glc
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT: buffer_gl1_inv
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX11-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/125255
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