[llvm] clastb representation in existing IR, and AArch64 codegen (PR #112738)

[Graham Hunter via llvm-commits]

huntergr-arm wrote:

@arsenm has the changed design addressed your concerns? The SDAGBuilder lowering is the same for all targets, and now I'm just marking the new ISD node as Legal for AArch64 to avoid the default vecops expansion here to improve SVE codegen.

https://github.com/llvm/llvm-project/pull/112738