[llvm] [AMDGPU] Allow unaligned VGPR for ds_read_b96_tr_b6 (PR #125169)

[Matt Arsenault via llvm-commits]

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@@ -4853,7 +4853,10 @@ bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
 
 bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
   auto FB = getFeatureBits();
-  if (!FB[AMDGPU::FeatureGFX90AInsts])
+  unsigned Opc = Inst.getOpcode();
+  // DS_READ_B96_TR_B6 is the only DS instruction in GFX950, that allows
+  // unaligned VGPR. All others only allow even aligned VGPRs.
+  if (!(FB[AMDGPU::FeatureGFX90AInsts]) || Opc == AMDGPU::DS_READ_B96_TR_B6_vi)
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arsenm wrote:

Extra parentheses. Also we probably should not directly special case the opcode here. This should come from the register class constraint of the operand 

https://github.com/llvm/llvm-project/pull/125169