[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,154 @@
+//===- RISCVVMV0Elimination.cpp - VMV0 Elimination -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// Mask operands in vector pseudos have to be in v0. We select them as a virtual
+// register in the singleton vmv0 register class instead of copying them to $v0
+// straight away, to make optimizing masks easier.
+//
+// However the register allocator struggles with singleton register classes and
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arsenm wrote:

This is a hand wavy and poor explanation for the problem and makes it sound like a workaround. The problem is primarily with every other piece of code that can now produce situations where multiple values must be live at the same time 

https://github.com/llvm/llvm-project/pull/125026