[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Philip Reames via llvm-commits]

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@@ -1515,40 +1515,36 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
 ; CHECK-NEXT:    vmv1r.v v0, v6
 ; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
 ; CHECK-NEXT:    vfabs.v v24, v16, v0.t
+; CHECK-NEXT:    addi a2, sp, 16
+; CHECK-NEXT:    vs8r.v v24, (a2) # Unknown-size Folded Spill
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preames wrote:

Huh?  We spill something, and then immediately fill it back to the same register?

(This is not new behavior, the prior code was actually worse.)

https://github.com/llvm/llvm-project/pull/125026