[llvm] [AArch64][SME] Make getRegAllocationHints more specific for multi-vector loads (PR #123081)

[Kerry McLaughlin via llvm-commits]

kmclaughlin-arm wrote:

> Would it make sense to update the title/commit message to reflect that you've also made it less strict? i.e. extracting one column from 4 x 2-vector loads can be used with an instruction that requires sequential regs now.

Thanks for approving this! I've reworded the title a bit and changed the commit message to include allowing x2 & x4 multivector loads and intrinsics.

https://github.com/llvm/llvm-project/pull/123081