[llvm] 83ca720 - PeepholeOpt: Remove check for reg_sequence def of subregister (#124512)

[via llvm-commits]

Author: Matt Arsenault
Date: 2025-01-30T20:55:48+07:00
New Revision: 83ca720ef280256ffb0424947e4221e95b314a09

URL: https://github.com/llvm/llvm-project/commit/83ca720ef280256ffb0424947e4221e95b314a09
DIFF: https://github.com/llvm/llvm-project/commit/83ca720ef280256ffb0424947e4221e95b314a09.diff

LOG: PeepholeOpt: Remove check for reg_sequence def of subregister (#124512)

The verifier does not allow reg_sequence to have subregister defs,
even if undef.

Added: 
    

Modified: 
    llvm/lib/CodeGen/PeepholeOptimizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index 2fc48209126acd..bf450e3af0deee 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1956,22 +1956,7 @@ ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
   assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
          "Invalid definition");
 
-  if (Def->getOperand(DefIdx).getSubReg())
-    // If we are composing subregs, bail out.
-    // The case we are checking is Def.<subreg> = REG_SEQUENCE.
-    // This should almost never happen as the SSA property is tracked at
-    // the register level (as opposed to the subreg level).
-    // I.e.,
-    // Def.sub0 =
-    // Def.sub1 =
-    // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
-    // Def. Thus, it must not be generated.
-    // However, some code could theoretically generates a single
-    // Def.sub0 (i.e, not defining the other subregs) and we would
-    // have this case.
-    // If we can ascertain (or force) that this never happens, we could
-    // turn that into an assertion.
-    return ValueTrackerResult();
+  assert(!Def->getOperand(DefIdx).getSubReg() && "illegal subregister def");
 
   SmallVector<RegSubRegPairAndIdx, 8> RegSeqInputRegs;
   if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))