[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

[Oliver Stannard via llvm-commits]

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@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp -mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
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ostannard wrote:

We should also test `-mcpu=cortex-r52+nofp.dp` (without `+nosimd`), this patch looks like it will also cause AdvSIMD to be disabled there, which I think is the right thing to do because there is no SP-only FPU with SIMD.

https://github.com/llvm/llvm-project/pull/124935