[llvm] [IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (PR #124825)

[Craig Topper via llvm-commits]

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@@ -1668,6 +1668,15 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
     return;
   }
 
+  if (getTypeAction(SubVecVT) == TargetLowering::TypeWidenVector &&
+      Vec.isUndef() && SubVecVT.getVectorElementType() == MVT::i1) {
+    SDValue WideSubVec = GetWidenedVector(SubVec);
+    if (WideSubVec.getValueType() == VecVT) {
+      std::tie(Lo, Hi) = DAG.SplitVector(WideSubVec, SDLoc(WideSubVec));
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topperc wrote:

There is a chance that's its been split. But since we don't depend on it yet, the topological sort the controls the visit order wouldn't know to guarantee it.

https://github.com/llvm/llvm-project/pull/124825