[llvm] [RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (PR #124678)

[Craig Topper via llvm-commits]

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@@ -57,6 +57,21 @@ class RISCVInstructionSelector : public InstructionSelector {
   const TargetRegisterClass *
   getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
 
+  static constexpr unsigned MaxRecursionDepth = 6;
+
+  // const MachineInstr &MI
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topperc wrote:

Drop this comment

https://github.com/llvm/llvm-project/pull/124678