[llvm] [SelectionDAG] Fix an incorrect DebugLoc on a COPY (PR #122963)

[Adrian Prantl via llvm-commits]

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@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s
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adrian-prantl wrote:

It would be more targeted to compile this with -stop-before=regalloc and check the MIR output instead of going all the way to assembler.

https://github.com/llvm/llvm-project/pull/122963