[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -6475,18 +6556,20 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(AArch64ISD::USDOT, dl, Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
   }
+  case Intrinsic::experimental_get_alias_lane_mask:
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sdesmalen-arm wrote:

This is no longer relevant, because the intrinsic is always lowered to a `EXPERIMENTAL_ALIAS_LANE_MASK` node by SelectionDAGBuilder?

https://github.com/llvm/llvm-project/pull/117007