[llvm] [RISCV] Add DAG combine for forming VAADDU_VL from VP intrinsics. (PR #124848)

[Philip Reames via llvm-commits]

preames wrote:

> This adds a VP version of an existing DAG combine. I've put it in RISCVISelLowering since we would need to add a ISD::VP_AVGCEIL opcode otherwise.

Not opposed to doing this in RISCV DAG, but an alternative in case you haven't considered it would be to emit a AVGCEIL node for the full type width (no predication), and then a VP.VSELECT just after it.  I believe the VLOptimizer should fold this back into the predicated form without issue.  This works for all instructions which are non-faulting (i.e. we can speculatively execute the additional lanes).  

https://github.com/llvm/llvm-project/pull/124848