[llvm] [AArch64] Codegen for new SCVTF/UCVTF variants (FEAT_FPRCVT) (PR #123767)

[via llvm-commits]

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@@ -5511,6 +5511,18 @@ multiclass IntegerToFPSIMDScalar<bits<2> rmode, bits<3> opcode, string asm, SDPa
     let Inst{31} = 1; // 64-bit FPR flag
     let Inst{23-22} = 0b00; // 32-bit FPR flag
   }
+
+  def : Pat<(f16 (op (i32 FPR32:$Rn))),
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CarolineConcatto wrote:

Why we need only this size? There is not need for f16-i64, f32-i64 or f64-i32?

https://github.com/llvm/llvm-project/pull/123767