[llvm] [PowerPC] Use SelectionDAG::makeEquivalentMemoryOrdering(). NFC (PR #124889)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 29 00:55:31 PST 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/124889
>From 28dd6d4aa813471717dbd034f0e6c1ab3d9315b4 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 28 Jan 2025 22:35:14 -0800
Subject: [PATCH 1/2] [PowerPC] Use
SelectionDAG::makeEquivalentMemoryOrdering(). NFC
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4ca328bd9a9ba2..1a325d92cb8145 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8651,22 +8651,13 @@ bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
// Given the head of the old chain, ResChain, insert a token factor containing
// it and NewResChain, and make users of ResChain now be users of that token
// factor.
-// TODO: Remove and use DAG::makeEquivalentMemoryOrdering() instead.
void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
SDValue NewResChain,
SelectionDAG &DAG) const {
if (!ResChain)
return;
- SDLoc dl(NewResChain);
-
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
- NewResChain, DAG.getUNDEF(MVT::Other));
- assert(TF.getNode() != NewResChain.getNode() &&
- "A new TF really is required here");
-
- DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
- DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
+ DAG.makeEquivalentMemoryOrdering(ResChain, NewResChain);
}
/// Analyze profitability of direct move
>From 756b2ce1a0fcd807ea32ebcd320e5ecb38782302 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 29 Jan 2025 00:53:51 -0800
Subject: [PATCH 2/2] fixup! remove helper
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 31 ++++++++-------------
llvm/lib/Target/PowerPC/PPCISelLowering.h | 2 --
2 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1a325d92cb8145..bdc1ac7c7da589 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8593,7 +8593,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
// to insert our load, L, into the chain as a peer of O. To do this, we give L
// the same chain operand as O, we create a token factor from the chain results
// of O and L, and we replace all uses of O's chain result with that token
-// factor (see spliceIntoChain below for this last part).
+// factor (this last part is handled by makeEquivalentMemoryOrdering).
bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
ReuseLoadInfo &RLI,
SelectionDAG &DAG,
@@ -8648,18 +8648,6 @@ bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
return true;
}
-// Given the head of the old chain, ResChain, insert a token factor containing
-// it and NewResChain, and make users of ResChain now be users of that token
-// factor.
-void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
- SDValue NewResChain,
- SelectionDAG &DAG) const {
- if (!ResChain)
- return;
-
- DAG.makeEquivalentMemoryOrdering(ResChain, NewResChain);
-}
-
/// Analyze profitability of direct move
/// prefer float load to int load plus direct move
/// when there is no integer use of int load
@@ -8921,7 +8909,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI,
RLI.Alignment, RLI.MMOFlags(), RLI.AAInfo, RLI.Ranges);
- spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
+ if (RLI.ResChain)
+ DAG.makeEquivalentMemoryOrdering(RLI.ResChain, Bits.getValue(1));
} else if (Subtarget.hasLFIWAX() &&
canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
MachineMemOperand *MMO =
@@ -8931,7 +8920,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
DAG.getVTList(MVT::f64, MVT::Other),
Ops, MVT::i32, MMO);
- spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
+ if (RLI.ResChain)
+ DAG.makeEquivalentMemoryOrdering(RLI.ResChain, Bits.getValue(1));
} else if (Subtarget.hasFPCVT() &&
canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
MachineMemOperand *MMO =
@@ -8941,7 +8931,8 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
DAG.getVTList(MVT::f64, MVT::Other),
Ops, MVT::i32, MMO);
- spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
+ if (RLI.ResChain)
+ DAG.makeEquivalentMemoryOrdering(RLI.ResChain, Bits.getValue(1));
} else if (((Subtarget.hasLFIWAX() &&
SINT.getOpcode() == ISD::SIGN_EXTEND) ||
(Subtarget.hasFPCVT() &&
@@ -9037,8 +9028,9 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
DAG.getVTList(MVT::f64, MVT::Other), Ops,
MVT::i32, MMO);
Chain = Ld.getValue(1);
- if (ReusingLoad)
- spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
+ if (ReusingLoad && RLI.ResChain) {
+ DAG.makeEquivalentMemoryOrdering(RLI.ResChain, Ld.getValue(1));
+ }
} else {
assert(Subtarget.isPPC64() &&
"i32->FP without LFIWAX supported only on PPC64");
@@ -11660,7 +11652,8 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SDValue Bits = DAG.getMemIntrinsicNode(
PPCISD::LD_SPLAT, dl, DAG.getVTList(MVT::v4i32, MVT::Other), Ops,
MVT::i32, MMO);
- spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
+ if (RLI.ResChain)
+ DAG.makeEquivalentMemoryOrdering(RLI.ResChain, Bits.getValue(1));
return Bits.getValue(0);
}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index cc01cab7a20897..514329bbe92d7f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1226,8 +1226,6 @@ namespace llvm {
bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
SelectionDAG &DAG,
ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
- void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
- SelectionDAG &DAG) const;
void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
SelectionDAG &DAG, const SDLoc &dl) const;
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