[clang] [llvm] [RISCV] Add a generic OOO CPU (PR #120712)

[Yingwei Zheng via llvm-commits]

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@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// We assume that:
+// * 6-issue out-of-order CPU with 192 ROB entries.
+// * Units:
+//   * IXU (Integer ALU Unit): 4 units, only one can execute division.
----------------
dtcxzyw wrote:

```suggestion
//   * IXU (Integer ALU Unit): 4 units, only one can execute multiplication/division.
```
In most RISC-V implementations, mul is handled separately. In general, the throughput of multiplication is less than that of other single-cycle instructions.



https://github.com/llvm/llvm-project/pull/120712