[llvm] [IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (PR #124825)

[Craig Topper via llvm-commits]

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@@ -10975,75 +10975,116 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
   assert(VecVT.isScalableVector() &&
          "vector_interleave on non-scalable vector!");
 
+  const unsigned Factor = Op->getNumValues();
+
   // 1 bit element vectors need to be widened to e8
   if (VecVT.getVectorElementType() == MVT::i1)
     return widenVectorOpsToi8(Op, DL, DAG);
 
-  // If the VT is LMUL=8, we need to split and reassemble.
-  if (VecVT.getSizeInBits().getKnownMinValue() ==
+  // If concatenating would exceed LMUL=8, we need to split.
----------------
topperc wrote:

This code doesn't handle fixed vectors which weren't possible with Factor==2, because SelectionDAGBuilder turns them into shuffles. But the SelectionDAGBuilder in this patch doesn't use shuffle for fixed vectors for factor 3, 5 or 7.

https://github.com/llvm/llvm-project/pull/124825