[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Sam Elliott via llvm-commits]

lenary wrote:

Can you talk (in a comment on this PR is fine) about how you see this fitting in with e.g. Zilsd support, which we were told is coming soon to upstream from NXP?

The NXP branch against 18.0 does similar things. IIRC, it has two load-store pairing passes (an early one and a late one), it makes changes to prolog-epilog inserter, and it might also make some changes directly to isel. Maybe some of these changes are useful to Mips' pairing instructions too? The NXP changes are here: https://github.com/llvm/llvm-project/compare/release/18.x...nxp-auto-tools:llvm-project:Zilsd/release/18.1.6 (this is a compare view of their 18.1.6 version against upstream release/18.x)

I would like to see coordination between you and NXP - maybe @anmolparalkar-nxp is the right person? - so that we can get a reasonably general load/store pair codegen implementation that can support extensions where the instruction details might be different, but the overall extensions are similar.

https://github.com/llvm/llvm-project/pull/124717