[llvm] [LoopVectorize][NFC] Disable output for tests that don't need it (PR #124747)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 28 05:47:07 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: David Sherwood (david-arm)
<details>
<summary>Changes</summary>
There are a lot of tests that do not depend upon the IR output
for validation, relying instead on the debug output. For these
tests we can add the -disable-output command line argument.
---
Patch is 271.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/124747.diff
141 Files Affected:
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/streaming-vectorization.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-outerloop-scevaddrec.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/loop-vect-memdep.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/nounroll.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-scalable.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/scalable-vf-hint.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/scalarized-bitcast.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/uncountable-single-exit-loops.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vect.stats.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll (+1-1)
``````````diff
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll
index 089d279d152455..ebc1f719203de1 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/no_vector_instructions.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -S -debug-only=loop-vectorize 2>&1 | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize -force-vector-interleave=1 -S -debug-only=loop-vectorize --disable-output 2>&1 | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-gnu"
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
index 1565d1ce982e3d..c4aee69db70b33 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
@@ -1,22 +1,22 @@
; REQUIRES: asserts
; RUN: opt -mtriple=aarch64 -mattr=+sve \
-; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
+; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output < %s 2>&1 \
; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
; RUN: opt -mtriple=aarch64 -mattr=+sve -mcpu=generic \
-; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
+; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output < %s 2>&1 \
; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v1 \
-; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
+; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output < %s 2>&1 \
; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING2
; RUN: opt -mtriple=aarch64 -mcpu=neoverse-n2 \
-; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
+; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output < %s 2>&1 \
; RUN: | FileCheck %s --check-prefixes=VSCALEFORTUNING1
; RUN: opt -mtriple=aarch64 -mcpu=neoverse-v2 \
-; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize < %s 2>&1 \
+; RUN: -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output < %s 2>&1 \
; RUN: | FileCheck %s --check-prefixes=NEOVERSEV2
; VSCALEFORTUNING1: Cost for VF vscale x 2: 11 (Estimated cost per lane: 5.
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
index e83eb729b521c2..dcb2b9b08d1e94 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
@@ -1,7 +1,7 @@
; REQUIRES: asserts
-; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize -scalable-vectorization=off < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_DISABLED
-; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize -scalable-vectorization=on < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_ON
-; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize -vectorizer-maximize-bandwidth -scalable-vectorization=on < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_ON_MAXBW
+; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output -scalable-vectorization=off < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_DISABLED
+; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output -scalable-vectorization=on < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_ON
+; RUN: opt -mtriple=aarch64-none-linux-gnu -mattr=+sve -force-target-instruction-cost=1 -passes=loop-vectorize -S -debug-only=loop-vectorize --disable-output -vectorizer-maximize-bandwidth -scalable-vectorization=on < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK_SCALABLE_ON_MAXBW
; Test that the MaxVF for the following loop, that has no dependence distances,
; is calculated as vscale x 4 (max legal SVE vector size) or vscale x 16
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/streaming-vectorization.ll b/llvm/test/Transforms/LoopVectorize/AArch64/streaming-vectorization.ll
index 924d4bfb7836ac..a26404eabedefb 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/streaming-vectorization.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/streaming-vectorization.ll
@@ -1,6 +1,6 @@
; REQUIRES: asserts
-; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,NOVEC
-; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize -enable-scalable-autovec-in-streaming-mode < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,VEC
+; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,NOVEC
+; RUN: opt -S -passes=loop-vectorize -debug-only=loop-vectorize --disable-output -enable-scalable-autovec-in-streaming-mode < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,VEC
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-outerloop-scevaddrec.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-outerloop-scevaddrec.ll
index 02bbfa839e6907..f118de1128a115 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-outerloop-scevaddrec.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-outerloop-scevaddrec.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -mattr=+sve2 -passes=loop-vectorize,instcombine -enable-histogram-loop-vectorization -sve-gather-overhead=2 -sve-scatter-overhead=2 -debug-only=loop-vectorize -S 2>&1 | FileCheck %s
+; RUN: opt < %s -mattr=+sve2 -passes=loop-vectorize,instcombine -enable-histogram-loop-vectorization -sve-gather-overhead=2 -sve-scatter-overhead=2 -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
; REQUIRES: asserts
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
index c119248c0be435..55f82fd55daf46 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-vplan.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -mattr=+sve2 -passes=loop-vectorize,instcombine -enable-histogram-loop-vectorization -sve-gather-overhead=2 -sve-scatter-overhead=2 -force-vector-interleave=1 -debug-only=loop-vectorize -S 2>&1 | FileCheck %s
+; RUN: opt < %s -mattr=+sve2 -passes=loop-vectorize,instcombine -enable-histogram-loop-vectorization -sve-gather-overhead=2 -sve-scatter-overhead=2 -force-vector-interleave=1 -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
; REQUIRES: asserts
target triple = "aarch64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
index aee0aa4b271f0c..44a48a9c262f51 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
@@ -1,7 +1,7 @@
-; RUN: opt -mtriple armv7-linux-gnueabihf -passes=loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
-; RUN: opt -mtriple armv8-linux-gnu -passes=loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
-; RUN: opt -mtriple armv8.1.m-none-eabi -mattr=+mve.fp -passes=loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=MVE
-; RUN: opt -mtriple armv7-unknwon-darwin -passes=loop-vectorize -S %s -debug-only=loop-vectorize -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=DARWIN
+; RUN: opt -mtriple armv7-linux-gnueabihf -passes=loop-vectorize -S %s -debug-only=loop-vectorize --disable-output -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
+; RUN: opt -mtriple armv8-linux-gnu -passes=loop-vectorize -S %s -debug-only=loop-vectorize --disable-output -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=LINUX
+; RUN: opt -mtriple armv8.1.m-none-eabi -mattr=+mve.fp -passes=loop-vectorize -S %s -debug-only=loop-vectorize --disable-output -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=MVE
+; RUN: opt -mtriple armv7-unknwon-darwin -passes=loop-vectorize -S %s -debug-only=loop-vectorize --disable-output -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=DARWIN
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
index 09a1aaab6cc2da..f68ffd1aea3cd0 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -riscv-v-vector-bits-min=128 -mattr="+v" -debug-only=loop-vectorize -S 2>&1 | FileCheck %s
+; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -riscv-v-vector-bits-min=128 -mattr="+v" -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
; CHECK: LV: Loop hints: force=enabled
; CHECK: LV: Scalar loop costs: 4.
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
index 71ee00fbf3ec5f..40d6e8bc334712 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -debug-only=loop-vectorize --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
; CHECK-LABEL: add
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
index c58307d9607869..e07c7b6b40729c 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll
@@ -1,6 +1,6 @@
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfh -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFH
-; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfhmin -debug-only=loop-vectorize -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFHMIN
+; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfh -debug-only=loop-vectorize --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFH
+; RUN: opt -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfhmin -debug-only=loop-vectorize --disable-output -riscv-v-register-bit-width-lmul=1 -S < %s 2>&1 | FileCheck %s --check-prefix=ZVFHMIN
define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {
; CHECK-LABEL: add
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
index 5e3de92bca8855..a2f55e49c9e0e4 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll
@@ -1,22 +1,22 @@
; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize \
+; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -force-vector-width=1 \
; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SCALAR
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize \
+; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=1 \
; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize \
+; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=2 \
; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize \
+; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=4 \
; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4
; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v,+d -debug-only=loop-vectorize \
+; RUN: -mattr=+v,+d -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=8 \
; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
index 95eb67b3823ee6..c332e2172b0777 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple riscv64-linux-gnu \
-; RUN: -mattr=+v -debug-only=loop-vectorize \
+; RUN: -mattr=+v -debug-only=loop-vectorize --disable-output \
; RUN: -riscv-v-vector-bits-min=128 -scalable-vectorization=off -S < %s 2>&1 | FileCheck %s
; CHECK-LABEL: foo
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
index 69418d9fea00ed..15f99931d165fe 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction-cost.ll
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize \
+; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize --disable-output \
; RUN: -force-tail-folding-style=data-with-evl \
; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
; RUN: -mtriple=riscv64 -mattr=+v -S < %s 2>&1 | FileCheck %s
diff --git a/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
index 1c427a0107df14..93d25a7ae94694 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "LV: Found an estimated cost of [0-9]+ for VF [0-9]+ For instruction:\s*%valB = load i16, ptr %inB, align 2"
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse2 --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=SSE
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse4.2 --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=SSE
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX1
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,-fast-gather --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-SLOWGATHER
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,+fast-gather --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-FASTGATHER
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx512bw --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX512
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse2 --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=SSE
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse4.2 --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=SSE
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=AVX1
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,-fast-gather --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-SLOWGATHER
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,+fast-gather --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-FASTGATHER
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx512bw --debug-only=loop-vectorize --disable-output < %s 2>&1 | FileCheck %s --check-prefixes=AVX512
; REQUIRES: asserts
diff --git a/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
index 8cde13761bc543..a23d57cfd4448c 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter "LV: Found an estimated cost of [0-9]+ for VF [0-9]+ For instruction:\s*%valB = load i32, ptr %inB, align 4"
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse2 --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=SSE2
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+sse4.2 --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=SSE42
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX1
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,-fast-gather --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-SLOWGATHER
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx2,+fast-gather --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX2-FASTGATHER
-; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr=+avx512bw --debug-only=loop-vectorize < %s 2>&1 | FileCheck %s --check-prefixes=AVX512
+; RUN: opt -passes=loop-vectorize -vectorizer-maximize-bandwidth -S -mattr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/124747
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