[llvm] [RISCV] Generate MIPS load/store pair instructions (PR #124717)

[Craig Topper via llvm-commits]

================
@@ -48,6 +48,7 @@ add_llvm_target(RISCVCodeGen
   RISCVISelLowering.cpp
   RISCVLandingPadSetup.cpp
   RISCVMachineFunctionInfo.cpp
+  RISCVLoadStoreOptimizer.cpp
----------------
topperc wrote:

alphabetize

https://github.com/llvm/llvm-project/pull/124717