[llvm] [RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (PR #124678)

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git-clang-format --diff ccd77953d0f1e367d268df89e7cc1c663c475ba7 211ddec6dda8f0f0282bf578e6b427af20442068 --extensions cpp -- llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 69cf1fd765..16f14c36ce 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -58,10 +58,17 @@ private:
   getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
 
   // const MachineInstr &MI
-  bool hasAllNBitUsers(const MachineInstr &MI, unsigned Bits, const unsigned Depth = 0) const;
-  bool hasAllBUsers(const MachineInstr &MI) const { return hasAllNBitUsers(MI, 8); }
-  bool hasAllHUsers(const MachineInstr &MI) const { return hasAllNBitUsers(MI, 16); }
-  bool hasAllWUsers(const MachineInstr &MI) const { return hasAllNBitUsers(MI, 32); }
+  bool hasAllNBitUsers(const MachineInstr &MI, unsigned Bits,
+                       const unsigned Depth = 0) const;
+  bool hasAllBUsers(const MachineInstr &MI) const {
+    return hasAllNBitUsers(MI, 8);
+  }
+  bool hasAllHUsers(const MachineInstr &MI) const {
+    return hasAllNBitUsers(MI, 16);
+  }
+  bool hasAllWUsers(const MachineInstr &MI) const {
+    return hasAllNBitUsers(MI, 32);
+  }
 
   bool isRegInGprb(Register Reg) const;
   bool isRegInFprb(Register Reg) const;
@@ -192,7 +199,9 @@ RISCVInstructionSelector::RISCVInstructionSelector(
 {
 }
 
-bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI, unsigned Bits, const unsigned Depth) const {
+bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI,
+                                               unsigned Bits,
+                                               const unsigned Depth) const {
 
   assert((MI.getOpcode() == TargetOpcode::G_ADD ||
           MI.getOpcode() == TargetOpcode::G_SUB ||

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https://github.com/llvm/llvm-project/pull/124678