[llvm] [AMDGPU][GlobalISel] Fix assert on APInt creation. (PR #124608)

[Daniil Fukalov via llvm-commits]

https://github.com/dfukalov updated https://github.com/llvm/llvm-project/pull/124608

>From 659517606b10f77e967d3ac5aca5c37585e315bd Mon Sep 17 00:00:00 2001
From: dfukalov <dfukalov at gmail.com>
Date: Mon, 27 Jan 2025 19:31:50 +0100
Subject: [PATCH 1/2] [AMDGPU][GlobalISel] Fix assert on APInt creation.

Since 3494ee95902cef62f767489802e469c58a13ea04 APInt stopped
to implicitly truncate values, therefore it asserts
on a big signed value converted to (implicitly) unsigned APInt.

The change explicitly marks offset as a signed value.
---
 llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp   |  2 +-
 .../AMDGPU/GlobalISel/assert-signed-apint.ll       | 14 ++++++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
index d64337c4cb9093..0b18c6b0e923a7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
@@ -56,7 +56,7 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
 
   Register Base;
   if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
-      KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
+      KnownBits->maskedValueIsZero(Base, APInt(32, Offset, /*isSigned=*/true)))
     return std::pair(Base, Offset);
 
   // Handle G_PTRTOINT (G_PTR_ADD base, const) case
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
new file mode 100644
index 00000000000000..33bdd67a42782e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
@@ -0,0 +1,14 @@
+; REQUIRES: asserts
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select -o - %s | FileCheck %s
+
+; 
+
+; CHECK-LABEL: @test
+; CHECK: S_BUFFER_LOAD_DWORD_SGPR_IMM
+
+define amdgpu_cs void @test(<4 x i32> inreg %base, i32 inreg %i, ptr addrspace(1) inreg %out) {
+  %off = or i32 %i, -2147483648
+  %v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0)
+  store i32 %v, ptr addrspace(1) %out, align 4
+  ret void
+}

>From 3023d8aa6b61ee0dd94720c51f711bb1992e64ac Mon Sep 17 00:00:00 2001
From: dfukalov <dfukalov at gmail.com>
Date: Mon, 27 Jan 2025 19:50:24 +0100
Subject: [PATCH 2/2] fixup! [AMDGPU][GlobalISel] Fix assert on APInt creation.

Add comment to test.
---
 llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
index 33bdd67a42782e..49344f7a0fd598 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
@@ -1,7 +1,7 @@
 ; REQUIRES: asserts
 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select -o - %s | FileCheck %s
 
-; 
+; Check that APInt doesn't assert on creation from -2147483648 value.
 
 ; CHECK-LABEL: @test
 ; CHECK: S_BUFFER_LOAD_DWORD_SGPR_IMM